In this era where energy-saving is high promoted, how to reduce power consumption of a chip has been a very concern currently. As is known to all, the power consumption of the chip is related to a working voltage. The higher the working voltage is, the greater the power consumption becomes. A minimum working voltage needed for the chip is dependent on critical paths in the chip, and the minimum working voltage needed for the chip changes with factors like temperature of the critical paths. When the chip works with a fixed working voltage, and yet the minimum working voltage needed for the chip is relatively low, unnecessary power consumption may be caused.
To keep the power consumption of the chip as low as possible, an adaptive voltage scaling (Adaptive Voltage Scaling, AVS for short) method is provided according to the prior art. Referring to FIG. 1, the chip 110 includes an adaptive voltage scaling AVS module 111 and a plurality of hardware performance monitors (Hardware Performance Monitor, HPM for short) 112 that are set in the vicinity of all critical paths respectively. The HPM 112 reflects in real time how corresponding critical paths in the chip 110 change with techniques, voltage, and temperature (PVT for short). The AVS module 111 acquires a current output value of the HPM 112 and compares the output value of the current HPM 112 with a reference value that is obtained through a test performed by an Automatic Test Equipment (Automatic Test Equipment, ATE for short). The reference value is an output value of the hardware performance monitor when the chip works with the minimum working voltage at any temperature. When the output value of the HPM 112 is smaller than a reference value, it indicates that a current working voltage of the chip 110 is too low, and therefore the AVS module 111 increases an output working voltage Vdd to the chip 110 by controlling an external power chip 120 by using a voltage interface 130. Otherwise, when the output value of the HPM 112 is bigger than or equal to the reference value, it indicates that the current voltage of the chip is too high, and therefore the AVS module 111 decreases the output working voltage Vdd to the chip 110 by controlling the external power chip 120 by using the voltage interface 130.
Referring to FIG. 2, the existing HPM 112 includes a generating module 1122 and a delay circuit 1121. Generally, the delay circuit 1121 includes a plurality of delay units 11211. When the AVS module 111 sends a clock signal to the HPM 112, the generating module 1122 of the HPM 112 inputs a corresponding pulse signal to the delay circuit 1121, and the delay circuit 1121 performs a delay on the input signal to generate an output value and sends the output value to the AVS module. To ensure that the output value of the HPM can correctly reflect how the corresponding critical paths in the chip 110 change with PVT, a Vt type of the delay unit 11211 of the delay circuit 1121 must be the same as the Vt type of the critical paths in the chip 110. For example, referring to FIG. 3, FIG. 3 shows minimum working voltages that different Vt types require at different temperatures. If the Vt type of the HPM 112, that is, the Vt type of the delay unit 11211 is UHVT, and the Vt type of the critical paths in the chip 110 is LVT, it may be easily known from FIG. 3 that in a state of −40° C., chip performance reflected by the HPM 112 is as follows: the minimum working voltage that the chip requires is 0.82 Volt (V) while the critical paths in the chip 110 only require 0.78 V. In this case, a waste of the power consumption is caused to the chip.
However, in the chip according to the prior art, a Multi-Threhold (Multi-Vt) technology is generally adopted to reduce the power consumption. Therefore, there can be different Vt types that correspond to different critical paths in the chip, and how to choose the Vt type of the delay unit in the HPM is a difficult problem. For example, standard cells of an SVT+HVT+UHVT type are adopted in a chip, and then a Vt type of different critical paths in the chip may be an SVT, HVT, or UHVT type. In this case, no matter which type of delay unit is selected for the HPM, performance of all critical paths in the chip cannot be accurately reflected. For example, as shown in FIG. 3, if a delay unit of the SVT type is selected for the HPM, at −40° C., chip performance reflected by the HPM is as follows: The working voltage that the chip requires is 0.79 V while the critical paths of UHVT type in the chip actually requires 0.82 V. If a delay unit of UHVT type is adopted the HPM, at −40° C., the chip performance reflected by the HPM is as follows: the working voltage that the chip requires is 0.82 V whereas the critical paths of UHVT type in the chip actually require 0.81 V.
In conclusion, based on the prior art, the HPM is simply not capable of correctly reflecting how all critical paths in a multi-Vt chip system change with PVT. Therefore, the AVS module fails to ensure reduction of the power consumption of the chip when the chip works normally at the same time.